Performance Comparisons of III-V and strained-Si in Planar FETs and Non-planar FinFETs at Ultra-short Gate Length (12nm)
Date of this Version4-2012
IEEE Transactions on Electron Devices (Volume: 59, Issue: 8, Aug. 2012)
The exponential miniaturization of Si CMOS technology has been a key to the electronics revolution. However, the downscaling of the gate length becomes the biggest challenge to maintain higher speed, lower power, and better electrostatic integrity for each following generation. Both industry and academia have been studying new device architectures and materials to address this challenge. In preparation for the 12nm technology node, this paper assesses the performance of the In0.75Ga0.25As of III-V semiconductor compounds and strained-Si channel nano-scale transistors with identical dimensions. The impact of the channel material property and device architecture on the ultimate performance of ballistic transistors is theoretically analyzed. 2-D and 3-D real-space ballistic quantum transport models are employed with band structure non-parabolicity. The simulation results indicate three conclusions: 1) the In0.75Ga0.25As FETs do not outperform strained-Si FETs, 2) triple-gate FinFETs surely represent the best architecture for sub-15nm gate contacts, independently from the material choice, and 3) The simulations results further show that the overall device performance is very strongly influenced by the source and drain resistances.
Nanoscience and Nanotechnology