Study of Ultra-Scaled SiGe/Si Core/Shell Nanowire FETs for CMOS Applications

Abhijeet Paul, Purdue University - Main Campus
Saumitra Mehrotra, Purdue University - Main Campus
Mathieu Luisier, Purdue University - Main Campus
Gerhard Klimeck, Purdue University - Main Campus

Date of this Version



2009 International Semiconductor Device Research Symposium: Study of ultra-scaled SiGe/Si core/shell nanowire FETs for CMOS applications


ISDRS 2009, December 9-11, 2009, College Park, MD


SiGe/Si core/shell nanowire (NW) devices are promising candidates for the future generation MOSFETs providing better channel control and hole mobility [1-4]. These core-shell devices can be exploited both as p- and n-type devices [3]. The Si shell improves the semiconductor-oxide interface and enhances the device performances [1, 3]. The Germanium condensation technique [4] is able to provide high Ge content (>50%) channel with Si as capping layer. In this work we investigate the viability of using these core/shell NWFETs for CMOS application.