Leakage-Reduction Design Concepts for Low-Power Vertical Tunneling Field-Effect Transistors

Samarth Agarwal, Purdue University - Main Campus
Gerhard Klimeck, Purdue University - Main Campus
Mathieu Luisier, Purdue University - Main Campus

Date of this Version



IEEE Electron Device Letters, Vol. 31, No. 6, pp. 621-623 (2010)


Using an atomistic full-band quantum transport solver, we investigate the performances of vertical band-to-band tunneling FETs (TFETs) whose operation is based on the enhance- ment of the gate-induced drain leakage mechanism of MOSFETs, and we compare them to lateral p-i-n devices. Although the ver- tical TFETs offer larger tunneling areas and therefore larger ON currents than their lateral counterparts, they suffer from lateral source-to-drain tunneling leakage away from the gate contact. We propose a design improvement to reduce the OFF current of the vertical TFETs, maintain large ON currents, and provide steep subthreshold slopes.


Nanoscience and Nanotechnology