Interface Trap Density Metrology from Sub-Threshold Transport in Highly Scaled Undoped Si n-FinFETs

Abhijeet Paul, NCN, Purdue University
Giuseppe C. Tettamanz, Kavli Institute of Nanoscience, Delft University
Sunhee Lee, NCN, Purdue University
Saumitra R. Mehrotra, NCN, Purdue University
Nadine Collaert, IMEC, Belgium
Serge Biesemans, IMEC, Belgium
Sven Rogge, Kavli Institute of Nanoscience, Delft University
Gerhard Klimeck, NCN, Purdue University

Date of this Version



Journal of Applied Physics 110, 124507 (2011)


arXiv:1102.0140v2 [cond-mat.mes-hall] 16 Feb 2011

Copyright (2011) American Institute of Physics. This article may be downloaded for personal use only. Any other use requires prior permission of the author and the American Institute of Physics. The following article appeared in Journal of Applied Physics 110, 124507 (2011) and may be found at The following article has been submitted to/accepted by Journal of Applied Physics. Copyright (2011) Abhijeet Paul, Giuseppe C. Tettamanzi, Sunhee Lee, Saumitra R. Mehrotra, Nadine Collaert, Serge Biesemans, Sven Rogge, and Gerhard Klimeck. This article is distributed under a Creative Commons Attribution 3.0 Unported License.


Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical Tight- Binding (TB) calculations, this technique can be used to understand the evolution of source-to- channel barrier height (Eb) and of active channel area (S) with gate bias (Vgs). The quantitative difference between experimental and theoretical values that we observe can be attributed to the interface traps present in these FinFETs. Therefore, based on the difference between measured and calculated values of (i) S and (ii) |∂Eb/∂Vgs| (channel to gate coupling), two new methods of interface trap density (Dit) metrology are outlined. These two methods are shown to be very consistent and reliable, thereby opening new ways of analyzing in situ state-of-the-art multi-gate FETs down to the few nm width limit. Furthermore, theoretical investigation of the spatial current density reveal volume inversion in thinner FinFETs near the threshold voltage.


Nanoscience and Nanotechnology