Interface Trap Density Metrology of State-of-the-Art Undoped Si n-FinFETs

Giuseppe Carlo Tettamanzi, Delft University of Technology, The Netherlands
Abhijeet Paul, NCN, Purdue University
Sunhee Lee, NCN, Purdue University
Saumitra R. Mehrotra, NCN, Purdue University
Nadine Collaert, IMEC, Belgium
Serge Biesemans, IMEC, Belgium
Gerhard Klimeck, NCN, Purdue University
Sven Rogge, Delft University of Technology, The Netherlands

Date of this Version



arXiv:1011.2582v1 [cond-mat.mes-hall] 11 Nov 2010


The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed structures. We present the first set of methods that allow direct estimation of Dit in state-of-the-art FinFETs, addressing a critical industry need.


Nanoscience and Nanotechnology