Interface Trap Density Metrology of State-of-the-Art Undoped Si n-FinFETs
Date of this Version11-11-2010
Giuseppe Carlo Tettamanzi, Abhijeet Paul, Sunhee Lee, Saumitra R. Mehrotra, Nadine Collaert, Serge Biesemans, Gerhard Klimeck, Sven Rogge. Interface Trap Density Metrology of State-of-the-Art Undoped Si n-FinFETs. IEEE Electron Device Letters (Volume: 32, Issue: 4, April 2011) DOI: 10.1109/LED.2011.2106150
The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed structures. We present the first set of methods that allow direct estimation of Dit in state-of-the-art FinFETs, addressing a critical industry need.
Nanoscience and Nanotechnology