Characterization and Modeling of Subfemotofarad Nanowire Capacitance Using the CBCM Technique
Date of this Version5-15-2009
The authors would like to thank Porf. M. S. Lundstrom at Purdue University, West Lafayette, IN, and Prof. G. Baccarani at the University of Bologna, Bologna, Italy, for the helpful discussions. The authors would also like to thank the staff of the SPT Laboratory, IME, Singaporre, for the support in fabricating the devices.
The experimental characterization of gate capacitance in nanoscale devices is challenging. We report an application of the charge-based capacitance measurement (CBCM) technique to measure the gate capacitance of a single-channel nanowire transistor. The measurement results are validated by 3-D electrostatic computations for parasitic estimation and 2-D self-consistent sp3s∗d5 tight-binding computations for intrinsic gate capacitance calculations. The device simulation domains were constructed based on SEM and TEM images of the experimental device. The carefully designed CBCM technique thus emerges as a useful technique formeasuring the capacitance and characterizing the transport in nanoscale devices.
Charge-based capacitance measurement (CBCM), nanowire MOSFETs, self-consistent C-V modeling, subfemtofarad-capacitance measurement