Nanoscale transistors: Physics and materials

Mark S. Lundstrom, School of Electrical and Computer Engineering, Birck Nanotechnology Center, Purdue University
Kurtis D. Cantley, Purdue University
Himadri S. Pal, Purdue University

Date of this Version



Network for Computational Nanotechnology, Dept. of Electrical and Computer Engineering, Purdue University


Symposium on Group 4 Semiconductor Nanostructures held at the 2006 MRS Fall Meeting Boston, MA, NOV 27-DEC 01, 2006


We analyze a modem-day 65nm MOSFET technology to determine its electrical characteristics and intrinsic ballistic efficiency. Using that information, we then predict the performance of similar devices comprised of different materials, such as higb-k gate dielectrics and III-V channel materials. The effects of series resistance are considered. Comparisons are made between the performance of these hypothetical devices and future generations of devices from the ITRS roadmap, including double-gate MOSFETs. We conclude that a Si channel device with a high-k gate dielectric and metal gate will outperform III-V channel materials for conventional CMOS applications, but will still not suffice in achieving long-term ITRS goals.