Current and Noise Properties of InAs Nanowire Transistors With Asymmetric Contacts Induced by Gate Overlap

Collin J. Delker, Purdue University, Birck Nanotechnology Center
Yunlong Zi, Purdue University
Chen Yang, Purdue University, Birck Nanotechnology Center
David B. Janes, Purdue University, Birck Nanotechnology Center

Date of this Version



Nanowire transistors are typically fabricated as geometrically symmetrical devices, with metal/semiconductor source and drain contacts rather than a graduated doping profile. While the source and drain contacts are nominally identical, contact asymmetry can arise when the gate contact is not centered over the nanowire, leaving uneven access regions with no gate coverage on one or both sides of the channel. Measuring the characteristics of devices with symmetric and asymmetric contact geometries allows contact effects to be studied. In this paper, indium arsenide nanowire transistors were fabricated with symmetric and asymmetric gate coverage. It is shown that devices with highly asymmetric gate coverage can exhibit a factor of 10 change in current and a shift in threshold of up to 0.5 V upon reversing the source-drain orientation. Devices with highly asymmetric properties show nearly identical channel-generated noise yet a significant difference in contact-generated noise levels when the contact orientation is reversed. Fully symmetric devices show higher current levels, lower threshold voltages, and lower contact-generated noise than asymmetric devices with either source or drain gated, but channel-generated noise levels are similar.


Nanoscience and Nanotechnology