Engineering Nanowire n-MOSFETs at L-g < 8 nm

Saumitra Mehrotra, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue University
SungGeun Kim, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue University
Tillmann Kubis, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue University
Michael Povolotskyi, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue University
Mark S. Lundstrom, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue University
Gerhard Klimeck, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue University

Abstract

As metal-oxide-semiconductor field-effect transistors (MOSFETs) channel lengths (L-g) are scaled to lengths shorter than L-g < 8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario, a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that different heavier transport masses can be engineered using strain and crystal-orientation engineering. Full-band extended device atomistic quantum transport simulations are performed for nanowire MOSFETs at L-g < 8 nm in both ballistic and incoherent scattering regimes. In conclusion, a heavier transport mass can indeed be advantageous in improving ON-state currents in ultrascaled nanowire MOSFETs.

Discipline(s)

Nanoscience and Nanotechnology