Single-walled carbon nanotubes (CNTs) are a potential channel material for the next generation field-effect transistors (FETs). With properties such as quasi-ballistic transport and high thermal conductivity, CNTFETs have the ability to outperform Si MOSFETs. To date, all reported CNTFETs have been created in a planar geometry, with the CNT horizontal to the supporting substrate. While planar CNTFETs have provided an important plaform for exploring device properties, they have yet to overcome the impending issues related to large-scale device fabrication. Obstracles such as precise placement, addressability, and high-density integration of CNTFETs can be overcome using a vertical device geometry. In the present work, vertical CNTs (v-CNTs) are synthesized within porous alumina templates and contacted in situ with vertical Pd nanowries. Semi-vertical CNTFETs are subjsequently fabricated to provide a comparison of the vertical nanowire contact to a more conventional planar content. Futher fabrication work is also presented, displyaing our progress towards fabricating addressable arrays of v-CNTFETs.
Carbon nanotubes (CNTs), field-effect transistors (FETs)
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