CMOS devices are evolving from planar to 3D non-planar devices at nanometer scale to meet the ITRS  scaling requirements. These devices will operate under strong confinement and strain, regimes where atomistic effects are important. This work focuses on the quantum effects on the electrostatics of ultra-scaled silicon nanowire transistors. The method is based on the calculation of nanowire dispersion using an atomistic tight-binding (TB) model (sp3d5s* -SO) coupled self-consistently to a 2D Poisson equation solver. We enable the understanding of atomistic treatment in the charge distribution as well as the capacitance measurements in these ultra-scaled silicon nanowire transistors. This work will enhance the already available Bandstructure Lab tool on nanoHUB.org.
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