Future military and commercial communication systems require a new generation of circuits with cognitive, deployable, agile, versatile, survivable, and sustainable capabilities. For these future system concepts to materialize, there is a need to substantially reduce size and cost and increase functionality and density, thus leading to high operating frequencies and wide bandwidths. However, at high frequencies and with wide analog and digital bandwidths, conventional chip-substrate integration techniques (e.g., solder bumps and wire-bonds) and filtering technologies limit system capability and compromise efficiency. The super-heterodyne radio architecture, most prevalent in present technologies, necessitates multiple passive offchip components including intermediate frequency (IF) filters adapted to the channel filtering requirements for various standards. Direct conversion (including low IF) architectures have evolved as they lend themselves to single- or few-chip mixed signal implementation, although performance may be compromised primarily, due to the direct current (dc) offset shift and the loss (finite Q) of on-chip passives leading to low radio frequency (RF) efficiency and high phase noise. In this circuit architecture, digital noise coupled into the RF circuitry further limits detectability. For future military communication systems, the above attributes must be obtained with performance superior to that available commercially and delivered with volumes relatively small in comparison to that in the commercial world. These performance requirements put a premium on heterogeneous wafer-scale integration whereby various optimized chip and component technologies can be combined to obtain improved overall performance.

Date of this Version

February 2007