In sub-micron CMOS design, non-minimum length transistors offer the possibility of achieving excellent leakage control without the disadvantages of other known leakage control techniques. Preliminary analyses indicate that one can expect leakage reduction by a factor of at least 100 (and possibly orders of magnitude higher) with only modest increases in circuit area and switched capacitance. This paper briefly reviews related leakage cor~trol techniques, describes the McCMOS technique, and presents :simulation results that are indicative of the performance of the technique.

Date of this Version

November 1997