Prevailing CMOS design practice has been very conservative with regard to choice of transistor threshold voltage, so as to avoid the difficult problems of threshold variations and high leakage currclnts. It is becoming necessary to scale threshold voltages more aggress~vely in order to obtain further power reduction, performance improven~ent, and integration density. Substantial leakage reduction can be achi~ved in single Vt designs by stacking low \.'t transistors. We have derived a simplified theoretical model which predicts the quiescent leakage current and the worst case time required to settle to quiescent levels in a single stack of transistors. This model can be used in a design environment to make quick estimation of leakage with respect to design changes. Model results are compared to circuit sirnulation. Leakage current predictions were found to rnatch simulation results very closely for a wide random selection of design parameter values and temperatures. Transistor stacks with mt~ltiple transistors turned off were found to have anywhere from 2 to 30 times lower leakage current than stack with only one transistor turned off. The time requirecl for a transistor stack to settle to quiescent current levels varied from a few microseconds up to tens of milliseconds.

Date of this Version

December 1997