In this report, we apply constraint least squares solution (CLS) to the problem of reducing the number of operations in FIR digital filters with a motivation of reducing its power consumption. The constraints are defined by the maximum allowable add/subtract operations in forming the products which are used in computing the output. We show that truncation and rounding 0.f coefficients can be viewed as power constrained least squares (PCLS) solutions. Further, we show that in dedicated DSP processor based architectures it is possible to reduce power by using PCLS coefficients along with appropriately modified multipliers. It is also shown that Booth multiplier effectively reduces the complexity of such filters, thereby increasing power savings. Finally, we show that typically 30% and 45% retluction in number of operations can be obtained for systems employing uncoded and Booth recoded multipliers, respectively.
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