Abstract
This work describes a significant new advance in the technique of silicon selective epitaxy called Confined Lateral Selective Epitaxial Growth (CLSEG). CLSEG is a method for forming thin films of single crystal silicon on top of an insulating layer or film. Such thin films are generically termed Silicon-On- Insulator (SOI), and1 allow dielectric isolation of integrated circuit elements, making them more efficient (faster with lower power), more resistant to radiation, and smaller than conventional integrated circuits, ionizing radiation than conventional integrated circuits. CLSEG offers advantages over current methods of achieving SOI by being easily manufactured, inherently reproducible, and having greater design flexibility. CLSEG is also adaptable to vertical stacking of devices in a circuit, in what is called three-dimensional integration, for even greater reductions in area. In addition, CLSEG can be used for a wide variety of sensor and micromachining application. This thesis describes the design and development of CLSEG, and compares it to the current state of the art in the fields of SOI and Selective Epitaxial Growth (SEG). CLSEG is accomplished by growing silicon selective epitaxy within a cavity; which is formed of dielectric materials upon a silicon substrate. The resulting SOI film can be made as thin as 0.1 micron, and tens of microns wide, with an unlimited length. In particular, there is now strong evidence that surface diffusivity of silicon adatoms on the dielectric masking layers is a significant contributor to the transport of silicon to the growth surface during SE G. CLSEG silicon material quality is evaluated by fabricating a variety of semiconductor devices in CLSEG films. These devices demonstrate the applicability of CLSEG to integrated circuits, and provide a basis of comparison between CLSEG-grown silicon and device-quality substrate silicon. Then, CLSEG is used to fabricate an advanced device structure, verifying the value and significance of this new epitaxy technique. In the final two chapters, CLSEG is evaluated as a technology, and compared to the current state of the art. Then, a method is presented Tor forming CLSEG with only one photolithography step, and a process is described for making a SOI film across an entire silicon wafer using CLSEG. These techniques may indicate the feasibility of using CLSEG for three dimensional integration of microelectronics. It is hoped that this work will establish a firm basis for further study of this interesting and valuable new technology.
Date of this Version
5-1-1990
Comments
PhD Thesis. This work was supported partly by Semiconductor Research Corporation contract number 90-SJ-108.