This work w ls supported partly by Semiconductor Research Corporation contract number 89-SJ-108 and Office if Naval Research # N00014-85-0438.


A three-dimensional silicon processing technology for CMOS circuits was developed and characterized. The first fully depleted SOI devices with individually biasable gates on both sides of the silicon film were realized. A vertically stacked CMOS Inverter built by lateral overgrowth was reported for the first time. Nucleation-free epitaxial lateral overgrowth of silicon over thin oxides was developed for both a pancake and a barrel-type epitaxy reactor: This process was optimized to limit damage to gate oxides and minimize dopant diffusion within the Substrate. Autodoping from impurities of the MOS transistors built in the substrate was greatly reduced. A planarisation technique was developed to reduce the silicon film thickness from 13μm to below 0.5μm for full depletion. Chemo-mechanical polishing was modified to yield an automatic etch stop with the corresponding control and uniformity of the silicon film. The resulting wafer topography is more planar than in a conventional substrate CMOS process. PMOS transistors which match the current drive of bulk NM0S devices of equal geometry were characterized, despite the three-times lower hole mobility. Devices realized in the substrate, at the bottom and on top of the SOI film were essentially indistinguishable from bulk devices. A novel device with two insulated gates controlling the same channel was characterized. Inverters were realized both as joint-gate configuration and with symmetric performance of n- and p-channel. These circuits were realized in the area of a single NMOS transistor.

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