Gallium Arsenide (GaAs) circuits have long been known for their speed. They are now being considered for single chip processors since GaAs chips are reaching VLSI complexities. Design constraints that affect both system and processor design accompany the new technology. The goal of this work is to compare and contrast designs in GaAs-E/D MESFET and Si-CMOS technologies as they apply to ALU design. These differences are emphasized by examining the design of several structures in GaAs for implementation of Stanford University’s MIPS processor in GaAs. The three topics discussed are adder design, multiplier placement and design, and cache effects on multiplier design. The comparisons were made to help optimize the design of 32-bit GaAs microprocessor for RCA. The results show that the high speed of GaAs devices allows serial rather than parallel implementation of structures in GaAs; these serial structures use less area than their parallel counterparts without any degradation of performance. The total reduction in area is necessary to compensate for the area used by large fanin and fanout structures. In addition, any solutions proposed for each structure must also take into account the long off-chip delays.
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