This research was supported in part, by research grant AFOSR-84-0385 and in part by Fujitsu Limited. From January 1985, the authors will be with Computer Research Institute, Dept. of Electrical Engineering, University of Southern California, Los Angeles, Calif. 90089. All rights are reserved by the authors, October 1984. A preliminary version of this paper was submitted for presentation at the 12th International Annual Symposium on Computer Architecture, Boston, Mass., June 17-19, 1985.


A dynamic network approach is introduced for developing reconfigurable, systolic arrays or wavefront processors; This allows one to design very powerful and flexible processors to be used in a general-purpose, reconfigurable, and fault-tolerant, multiprocessor computer system. The concepts of macro-dataflow and multitasking can be integrated to handle variable-resolution granularities in computationally intensive algorithms. A multiprocessor architecture, Remps, is proposed based on these design methodologies. The Remps architecture is generalized from the Cedar, HEP, Cray X- MP, Trac, NYU ultracomputer, S-l, Pumps, Chip, and SAM projects. Our goal is to provide a multiprocessor research model for developing design methodologies, multiprocessing and multitasking supports, dynamic systolic/wavefront array processors, interconnection networks, reconfiguration techniques, and performance analysis tools. These system design and operational techniques should be useful to those who are developing or evaluating multiprocessor supercomputers.


Systolic, arrays, wavefront arrays, interconnection networks, macro dataflow, multitasking, reconfiguration techniques, supercomputer performances.

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