The objective of this work is to study the defects of the SEG/insulator sidewall interface as applied to the novel 3-dimensional structures. The defects were characterized through electrical measurements of a p+/n diode and transmission electron microscopy. Different mechanisms have been postulated to be responsible for these defects. These include thermal stress induced defects, defect nucleation close to the sidewall, and defects at the interface due to weak bonding. The simple structure of the diocie allowed the design of many experiments in order to study the dependence of the sidewall defects on process conditions and other parameters and to identify the mechanisms controlling these defects. A novel 3-dimensional BiCMOS technology and a new triple self-aligned bipolar junction transistor were also presented as a further motivation to study the sidewall defects. The 3-D BiCMOS technology and triple aligned BJT utilize a structure where the base/collector junction and depletion region will intersect the epitaxial silicon/oxide sidewall interface. For successful operation of the BJTs, it is necessary to characterize, quantify, and control these sidewall defects. It was discovered that the sidewall defects are caused mainly due to the thermal mismatch between the silicon and the insu1ator. A model predicting the generation of defects due to thermal stress was described. The sidewall defects are also generated due to a rough interface caused by the degradation of the insulator. A systematic study of the degradation of various insulators was performed and it was found that nitrided oxides were more resistant to SEG ambient than thermal oxides.

Date of this Version

December 1992