In this paper a new algorithm for discrete cosine transform (DCT) is proposed. This algorithm is especially efficient for VLSI implementation because each multiplier in @e 1-D DCT is shared by two constants rather than one. This greatly reduces the chip area, and the high speed characteristics are still retained. Based on this algorithm, we have developed the corresponding bit-parallel, fully-pipelined architecture for the size-8 DCT. The core area of the chip is only 8.6mm x 8.5mm, using 1.2um double-metal single-poly CMOS technology. This chip is simulated for operation at the maximum speed of 100 MHz which far exceeds the speed requirement of the HDTV system (70 MHz).

Date of this Version

September 1992