In this paper we address the problem of optimization of VLSI circuits to minimize power consumptioin while meeting performance goals. We present a method of estimating power consumptioin of a basic or complex CMOS gate which takes the internal cap,acitances of the gate into account. This method is used to select an ordering of series-connected transistors found in CMOS gates to achieve lower power consumption. The method is very efficient when used by library based design styles. We describe a multi-pass algorithm which makes use of transistor reordering to optimize performance and power consumption of circuits, which has a linear time complexity per pass and which converges to a solution in a small number of passes. Transformations besides transistor reordering can be used by the algorithm. The algorithm has been benchmarked on several large examples and the results are presented.
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