Although it is convenient to program multiprocessors as though all processors share access to the same memory, it is difficult to construct hardware directly implementing this model. Allowing each processor to have its own independent cache partially solves this problem; unfortunately, different caches might hold different values for the same main memory address. Making the cache hardware always be coherent - one value per address - makes the hardware expensive and slow. This paper proposes compiler analysis to generate explicit cache control instructions to ensure that all program memory accesses execute as though the caches were coherent. Compared to other approaches, the method given in this paper is superior because the analysis more accurately models interactions between tasks.


Cache Coherence, Cache Policy, Compiler Optimization, Shared Memory, MIMD

Date of this Version

January 1993