We present a new logic family, Differential Current Switch Logic (DCSL) for implementing clocked CMOS circuits. The circuit is in principle a differential cascode voltage switch logic circuit (DCVS). In cornparimsonto other forms of' clocked DCVS, DCSL achieves better performance both in terms of power and speed by restricting internal voltage swings in the N tree. Automatic lock-out of inputs on completion of evaluation is a novel feature of the circuit and allows new implementation of logic functions and the possibility of operating with reduced voltage swings. SPICE simulattions carried out with. the MOSIS 1 . 2 process indicate that DCSL is better than similar clocked DCVS circuits by a factor of two both in terms of power and speed, for moderate tree heights.
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