In the design of low-power circuits, adiabatic logic shows great promise. However, research till date have concentrated on adiabatic logic circuits/families. Today's VLSlsystems integrate random logic, megamodules and memories. Hence, the success of adiabatic circuits will depend on the efficient implementation of not only random logic, but also the other components of a VLSI system. In this paper, we present a design of adiabatic Static RAM, which can be implemerited withorit greatly increasing area or circuit complexity. The design addresses the issue of building ultra-low power memory circuits in a VLSI system. Our results for a 41

Date of this Version

April 1996