In this paper, we provide the first systematic and comprehensive analysis of off-state degradation in Drain-Extended PMOS transistors - an enabling input/output (I/O) component in many systems and a prototypical example of devices with correlated degradation (i.e., hot carrier damage leading to gate dielectric failure). We use a wide range of characterization tools (e.g., Charge-pumping and multi-frequency charge pumping to probe damage generation, IDLIN measurement for parametric degradation, current-ratio technique to locate breakdown spot, etc.) along with broad range of computational models (e.g., process, device, Monte Carlo models for hot-carrier profiling, asymmetric percolation for failure statistics, etc.) to carefully and systematically map the spatial and temporal dynamics of correlated trap generation in DePMOS transistors. Our key finding is that, despite the apparent complexity and randomness of the trap-generation process, appropriate scaling shows that the mechanics of trap generation is inherently universal. We use the universality to understand the parametric degradation and TDDB of DePMOS transistors and to perform lifetime projections from stress to operating conditions.


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electric breakdown, hot carriers, MOSFET

Date of this Version

January 2008



Published in:

2008 IEEE International Reliability Physics Symposium (IRPS) (2008) 566-74;



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