MICHEL DUBOIS, Purdue University


Interest in multitasked multiprocessor systems is motivated by the necessity to increase throughput and speed-up beyond the limitations of current technology. The potential of various multiprocessing structures for improving the speed-up of job execution through multitasking for given classes of algorithms is investigated. In tightly coupled systems, performance is affected by memory interference. Conversely, the cost of interprocessor communication is determinant for loosely coupled systems. The relative effects of synchronization, memory conflicts and interprocessor communication for synchronized interative algorithms are estimated using analytical solutions to stochastic functional models. A general performance model of asynchronous algorithms based on the central server model is developed for tightly coupled systems, in order to evaluate the relative effects of the sharing of critical sections and of memory conflicts. The model is particularly adequate for studying systems with processes sharing critical sections with low coefficients of variation.^ In many commercial multiprocessor systems, each processor accesses the shared memory through a private cache. Important features for algorithms running on cache-based systems are the locality (measured by the hit ratio), the fraction of writes versus reads and the degree of sharing of data blocks between the caches. The sharing of blocks introduces the problem of cache coherence. An in-depth analysis of the effects of cache coherency in multiprocessors is presented. A novel analytical model for the program behavior of a multitasked system is developed. This model includes the behavior of each process and the interactions between processes with regard to the sharing of data blocks. An analytical approximation is derived to evaluate the main effects of the cache coherency contributing to degradations in system performance. Finally, alternate design decisions for a cache-based multiprocessor are examined in detail. A multiprocessor with private caches and a shared memory assuming the L-M organization is proposed. The shared memory is interleaved and pipelined, to improve the block transfer rate. Models are developed for fully associative and set-associative cache organizations. The systems with and without caches are then compared in order to show the effectiveness of caches in multiprocessors. ^



Subject Area

Engineering, Electronics and Electrical

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