YAO-YANG HSIEH, Purdue University


Today, integrated circuits are fabricated with more and more devices existent on a unit area. Consequently, the inspection of such a complicated circuit poses a critical problem. A detailed visual inspection is the most effective method to screen out unreliable IC's. But such a labor-intensive task is not suitable to be done by human operators. Also, the alignment and wire-bonding of integrated circuit are not yet fully automated. Consequently, the visual inspection process and the wire-bonding process constitute the bottle-neck of IC production. To automate these processes by means of pattern recognition and image processing techniques is a challenge. A formulation of an automatic visual inspection and final packaging system is presented in this thesis. Such a system is composed of three subsystems: (1) the image segmentation and registration subsystem, (2) the visual inspection subsystem, and (3) the final packaging subsystem. The information within the visual inspection subsystem flows among three parts: (1) the visual inspection controller, (2) the design and inspection specification data base, and (3) the library of algorithms. The inspection controller decomposes the inspection job into smaller tasks. For each task, the controller activates a program fetched from the program library to operate on the sensed data by consulting the appropriate reference data. At the end of a task, the controller makes a decision of what to do next, depending on the result of the task. At last, the controller generates a report of the inspection and stops. An integrated system for automatic visual inspection and wirebonding of integrated circuits is proposed in this thesis. The structure of such an integrated system follows the above general formulation. The functions of the image segmentation and registration subsystem include image segmentation, gross registration, and the microregistration of mask subpatterns. The input image S is first decomposed into the image W of the IC chip and the background. The gross registration of the IC chip is achieved by locating the mask frame. But since an IC image is a multi-layer image, each mask subpattern has to be micro-registered independently. The functions of the visual inspection subsystem include image transformation, detection and identification of IC defects, and classification. The idea of image transformation is to emphasize relevant information and to suppress irrelevant information. Furthermore, contextual information is made use of to remove ambiguity. Each IC defect is to be detected by an individual defect detector. Finally, the IC under inspection is classified into three classes: (1) accept, (2) reject, and (3) to be reworked. The final packaging subsystem solders an acceptable IC chip to the package substrate, detects the misregistration introduced during the soldering process, and then carries out the wire-bonding. Such an integrated system proposed in this thesis is proved to be successful by experimental results.



Subject Area

Electrical engineering

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