Nonvolatile Cache and Flip-Flop Design for Low Standby Leakage SoC

Kon-Woo Kwon, Purdue University


As CMOS technology scales down, the leakage power in high-performance microprocessor can exceed 40% of the total power consumption. In order to reduce the leakage power consumption, there is a need to explore nonvolatile on-chip memory and logic designs. To address the aforementioned issue, this research presents two designs: spin-transfer torque magnetic RAM (STT-MRAM) cache and spin Hall effect based nonvolatile flip-flop (SHE-NVFF). STT-MRAM, in which a magnetic tunnel junction (MTJ) is used as the storage element, has become a leading candidate for on-chip caches due to its desirable memory characteristics such as nonvolatility, near zero standby leakage power and compatibility with CMOS fabrication process. However, retention/write/read failures in STT-MRAM negatively impact the memory yield, density and dynamic energy consumption. We propose a device-circuit-architecture co-design methodology, which jointly considers MTJ retention capability, STT-MRAM bitcell characteristics and various architectural techniques (error correcting codes, scrubbing and invert-coding) at different levels of design abstraction so as to maximize memory density while meeting the yield requirement and improving the energy consumption. We also propose an MTJ-based NVFF for power gating architecture. The proposed NVFF exploits SHE for fast and low power data backup into MTJs before the power is turned off. Owing to the high spin injection efficiency of SHE, the write current for backup operation is lower than that in previous work using STT. Due to the low write current requirement, we re-use the cross-coupled inverters in the slave latch to perform the backup operation, resulting in low area overhead.




Roy, Purdue University.

Subject Area

Electrical engineering

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