Capacitance-based characterization of inhomogeneities in thin layers
In this work, capacitance-based sensing is investigated for characterizing the morphology of dielectric inhomogeneities in high aspect-ratio planar domains. The work is motivated by the need for in situ experimental characterization of void development in a layer of dielectric thermal interface material under realistic operating conditions. The sensing methods are applicable to phase characterization in other media such as polymer sheets or dielectric fluids in narrow microfluidic channels. First, an orthogonal mesh sensor configuration is investigated, which requires a rake of embedded electrodes in each of two confining substrates. Substrates are oriented to create a grid of crossing points. Capacitance measurements at each crossing point are used to interrogate the material under test (MUT). In an electrically floating configuration, the system gives rise to a nontrivial capacitance network, which must be solved in reverse to correctly map inhomogeneities. In a grounded configuration, electrodes other than the active pair are maintained at virtual ground during each measurement. Detection of inhomogeneities approximately 200 ?m in diameter are demonstrated in thin (25–250 µm) MUTs. Next, a sensor configuration with an array of electrodes in one substrate and a single large electrode on the opposing substrate is investigated. When the MUT is comparatively thick (~1 mm), capacitance measurements taken between neighboring coplanar pairs in the array and between facing pairs also provide useful information. Electrical capacitance tomography (ECT) using this setup is demonstrated on a 1.27 mm-thick MUT. Alternatively, when the MUT is thin (? 200 ?m), measurements between coplanar pairs do not provide useful information, but measurements obtained from opposing pairs may be used to reconstruct a map of non-uniform MUT thickness, as might occur due to substrate tilting or warpage, in addition to a map of local void content. Reconstruction of both thickness and voiding maps in a thermal grease confined by tilted substrates is demonstrated experimentally. A theoretical investigation of the effectiveness of double-sided electrode configurations for thick MUTs is also conducted. Simulated tomography is conducted using different electrode designs patterns. It is shown that an optimum electrode size may be identified, which depends on signal-to-noise ratio of the system. Patterns with a lateral offset between the arrays are generally superior to their aligned counterparts. Throughout this investigation of the capacitive sensing methods, image reconstruction algorithms are developed which are tailored to the different sensor types. A level-set shape reconstruction algorithm for mapping local void fractions is developed, which dramatically improves visualization compared to a map of tessellated, grayscaled void fractions. A strictly binary image algorithm for ECT on large meshes is developed, termed the shape-energy evolution reconstruction (SEER) algorithm. The SEER algorithm developed in this work provides an efficient methodology for reconstructing purely binary images while forcefully regularizing the image reconstruction process in severely underdetermined systems. Next, an explicitly regularized solution for general ECT, sensitivity factor regularization (SFR), is presented. The SFR algorithm is shown to perform better than other explicit methods, including linear back projection and Tikhonov regularization, and is ideal for conducting design studies on 2D systems using electrode density as a design variable. Also, a distinguishing algorithm is developed for obtaining maps of both of MUT thickness and void content over the footprint of a joint from a single map of capacitance measurements.
Garimella, Purdue University.
Electrical engineering|Mechanical engineering
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