Multicore memory system architectures for programmability and verifiability
For power and performance reasons, multicores have become the dominant microprocessor architecture. However, multicores have many components (e.g., caches and cores) whose interactions are timing dependent. As a result of this non-determinism, multicores exhibit both software and hardware bugs. On the software side, multicores run shared-memory parallel programs which suffer from non-deterministic bugs. Such bugs are difficult to reliably replicate during debug executions. Further, writing parallel programs is prone to errors such as unintended data races, livelocks, and deadlocks. On the hardware side, multicores employ coherence protocols to facilitate communication between cores. However, the many interacting components lead to complex, error-prone protocols. Verifying a protocol involves checking each of the system's states, the count of which increases exponentially with the number of components (e.g., cores). Thus, the verification effort increases with system scale. Further, every time the system size increases, the protocol must be re-verified. Existing protocols are either not scalably verifiable (most existing protocols) or are verifiable but do not scale well in performance (e.g., fractal coherence). In my thesis I propose new memory system architectures to address the above software programmability and hardware verifiability problems. Specifically, to address the difficulty of debugging and writing parallel programs, I propose a low-overhead hardware record-and-replay system and architectural support for a high-performance transactional memory system, respectively. To address the difficulty of scalably verifying coherence protocols, I propose a high-performance fractal coherence protocol.
Vijaykumar, Purdue University.
Computer Engineering|Computer science
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