Circuits and systems for hybrid inter- and intra-chip interconnects
With the scaling of CMOS technology, transistor performance is improving but interconnects are becoming the limiting factor for power and performance by imposing limits on communication latency between cores and memories, both on- and off-chip. Wireless interconnects can help improve the performance of wireline systems. This dissertation proposes utilizing a hybrid wireline/wireless interconnection for two applications - intra-chip communication for chip-multiple processor designs, and interchip data communication and wireless testing in 3-D SIC designs. For intra-chip communication system, micro-scale communication networks have physical constraints such as antenna size and available energy resources. A perspective of using inductive-coupled wireless links in cooperation with locally wired links for core-to-core communications in network-on-chip system is proposed. The 8-Gbps wireless front-end is implemented with little area and power overhead. The trade-offs of this topology have also been investigated by a network simulator which demonstrates a maximum 34-% latency reduction for 8×8 network compared to standard mesh network. As for inter-chip communication, wireless interconnects utilizing integrated meandering microbump antenna in 3-D SICs with mm-wave transceiver circuit is proposed and designed. The proposed compact antenna provides 133-% wider bandwidth with 23-% and 16-% improvements in gain and radiation efficiency compared to on-chip 2-D antenna. The wireless transceiver with CDR achieves 8-pJ/bit energy efficiency and 10Gbps data rate. The research addresses several important and challenging issues of data link and wireless testing in 3-D SICs. This opens an interesting paradigm of utilizing the wireless I/Os in future high-performance 3-D SIC systems to improve system testability and connectivity.
JUNG, Purdue University.
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