Aggressive voltage scaling in digital circuits
Abstract
Due to quadratic dependence of switching power on supply power, supply scaling leads to significant power savings. However, as the supply voltage is lowered, drive current of a MOSFET becomes more sensitive to PVT variations, resulting in many challenges in the design of digital circuits. This research mainly focuses on PVT tolerant design of digital circuits such as memory and logic in ultra-low voltage operation. In memory, low supply voltage results in read stability problems. Recently, an 8T bit-cell was developed to improve the read stability. However, its application is limited due to large area penalty (above 30%). We propose a hybrid SRAM architecture for video memory, where only critical MSB bits are stored in the 8T bit-cells. This approach allows 200mV over-scaling of VDD (to 600mV) without compromising image quality while incurring only 11.5% area overhead. To achieve ultra-low power dissipation, we lowered memory supply more aggressively (below 300mV VDD). Under such an ultra-low voltage, the 8T bit-cells, however, fail to deliver yield requirements due to small bit-line swing and vulnerability to soft-errors. To address these issues, we propose a differential 10T bit-cell. Hardware measurement results show that 32kb array of the proposed 10T bit-cell operates successfully at 160mV VDD. In the second part of this research, we focus on ultra low voltage logic design. We designed a dynamic level converter, enabling us to communicate between ultra-low voltage core logic and high voltage (2.5V) I/O circuits. To obtain high energy efficiency and process tolerance in ultra-low operation of core logic, we explored asynchronous design techniques. We fabricated an 8-tap FIR filter using this technique. The measured results demonstrated robust ultra-low voltage operation (below 300mV V DD) -- the measured minimum energy dissipation was 4.46pJ.
Degree
Ph.D.
Advisors
Roy, Purdue University.
Subject Area
Electrical engineering
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