Architecture-aware circuit design for process tolerance and resilience
Abstract
Aggressive technology scaling is leading to large variations in transistor parameters due to process imperfections. These variations have led to significantly diminished yields. Conventional design methodologies to alleviate the effects of variations typically involve either lowering the operation frequency, which leads to lower performance, or increased voltage margins, which lead to higher power dissipation. This research leverages the observation that only a small set of operations actually fail under variations when the conventional design methodology is used. Hence, instead of scaling the frequency of the whole system, corrective action is required only for the failing operations. By obviating the need for lowering the frequency or additional voltage margins, this design methodology improves yield while ensuring that area, power, and performance overhead is very small. The methodology been applied to SRAM cache design for improved yield, and has been extended to Spin-Torque Transfer MRAM (STT MRAM). In addition, it has been applied for improved yield and fault tolerance in microprocessor design.
Degree
Ph.D.
Advisors
Roy, Purdue University.
Subject Area
Electrical engineering
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