Vertical devices from single-walled carbon nanotubes templated in porous anodic alumina
Over the past decade, tremendous progress has been realized in the fabrication and characterization of single-walled carbon nanotube (CNT) electronic devices. For example, with advantages such as ballistic transport and the absence of surface states, CNTs have been proposed as an ideal 1D channel material for next generation field-effect transistors (FETs). However, the literature is replete with reports of individual high-performance devices that lack the demonstration or feasibility of being fabricated at a large scale. One of the primary obstacles to fabricating highly integrated CNT devices is the placement of the nanotubes at a defined spacing and in precise locations. Nearly all CNT devices to date have been configured in a planar geometry (with the CNT supported horizontally on a substrate) and have primarily relied on random processes for dispersing/growing and contacting the CNTs. Ideally, a high-performance CNTFET would consist of multiple, densely packed CNTs that are aligned, having surround gates, low-barrier contacts, and a sub-100 nm channel length. Such multi-nanotube CNTFETs should further be fabricated in a manner that can be scaled for high-level integration and that is compatible with modern CMOS processing. This dissertation describes the development of a platform based on vertically aligned CNTs templated in porous anodic alumina (PAA) for the scalable fabrication of multi-nanotube CNTFETs with surround gates as well as several other nanoelectronic devices. PAA is a template consisting of hexagonally ordered pores that result from the anodization of an Al film. By embedding a catalyst layer within PAA, single-walled CNTs are synthesized from the nanoscale vertical pores (pore diameter ≈20 nm, spacing ≈100 nm) at a yield of no more than one nanotube per pore. After synthesis, the CNTs are contacted within the pores by electrodepositing Pd, a known low-barrier contact metal for CNTs, to form nanowires that electrically address the CNTs near their nucleation sites. Using a combination of deposition and etching processes, gates are then formed that completely surround the vertically aligned CNTs to obtain optimal channel electrostatics. The low cost and high-throughput nature of the processes used for fabricating these surround-gated CNTs is highly advantageous in the context of manufacturing multi-nanotube FETs. The processes of CNT growth, gate dielectric deposition, metal deposition, and channel length definition down to 50 nm across all devices on a chip can potentially be realized using rapid and inexpensive processes compared to the more commonly used post-synthesis dispersion of CNTs combined with electron-beam lithography. In addition to their application in surround-gated CNTFETs, other applications of this PAA-templated-CNTs platform are demonstrated, including their use in biosensing, noise thermometry, and electron emission.
Janes, Purdue University.
Physical chemistry|Electrical engineering|Molecular physics
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