Low complexity digital signal processing system design techniques

Jong-sun Park, Purdue University


Complexity reduction in the Digital Signal Processing (DSP) system design has been of particular interest since lower computational complexity leads to high performance and low power design. In this work, we present low complexity DSP design techniques. The first part of this work is about low complexity finite impulse response (FIR) filter and discrete cosine transform (DCT) architectures based on computation sharing multiplier (CSHM) scheme. The main idea of CSHM is to represent the multiplications in vector-scalar products as a combination of add and shift operations over the common computation results. The common computations are identified and are shared without additional memory area. Low power and high performance programmable FIR filter and DCT are efficiently implemented using the CSHM scheme. In the second part, we propose low complexity reconfigurable DCT architectures which are based on the image quality and computation energy trade-off approach. Two ideas are presented for the efficient trade-off between image quality and computational complexity. The first approach adopts the DCT bases modification in a bit-wise manner with minimum image quality degradation. Using sensitivity differences of non-zero digits in DCT bases, new quantization method is proposed in this approach. The second one is based on dynamic bit-width adaptation, where operand bit-widths are changed according to the image quality and/or power consumption requirements. Using the proposed schemes, various trade-off levels are proposed and the proposed DCT architecture can be dynamically reconfigured from one trade-off level to another with negligible overhead. Low-complexity DSP system design techniques are also applied for 1/ fα noise generation in the final part of this thesis. The architecture is based on multi-rate filter bank. Using the filter bank approach, a single filter with a large number of filter taps can be equivalently implemented with a parallel combination of much shorter subband filters. This scheme greatly reduces computation when compared to traditional noise generation approach of using a single noise shaping filter. Furthermore, it allows selection of different combinations of noise frequency response in different frequency bands, thus allowing calibration of noise generated in simulation to the one measured in the laboratory from test chips.




Roy, Purdue University.

Subject Area

Electrical engineering

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