Process variation aware high performance low power VLSI system design in nano-scale regime

Amit Agarwal, Purdue University


As the CMOS technology continues to scale down for higher performance, power dissipation and robustness to leakage, noise, and process variations are becoming major obstacles for circuit design in the nano-scale regimes. Due to increased density of transistors in a die and higher frequencies of operation, the power consumption is reaching the cooling capacity limits. On the other hand, due to increased leakage, noise, and process variations, the predictability and therefore the design yield is threatened. This thesis focuses in the cooperative field of circuit/device and circuit/architecture co-design for high-performance and low-power VLSI systems in the nanometer regime considering process variation. We first analyze the impact of process variation on the different failure mechanisms in SRAM cells and propose a fault tolerant cache architecture suitable for high performance memory. This technique dynamically detects and replaces faulty cells by adaptively resizing the cache. Next, we present a pipelined cache architecture which can be accessed every clock cycle and thereby, enhances bandwidth and overall processor performance. The proposed architecture utilizes the idea of banking to reduce bit-line and word-line delay, making word-line to sense amplifier delay to fit into a single clock cycle. Next, we propose a leakage tolerant, high performance register file design targeted for sub-90nm technology generations. A wordline under-drive technique combined with local bitline merge NAND whose P/N skew is optimally programmable based on die leakage showing good promise for squeezing the robustness and delay distribution is described. We also present a low leakage, leakage tolerant register file using conditional sleep transistor. The local bitline shares a sleep transistor for aggressive bitline leakage reduction/tolerance to enable high fanin bitlines with low-V t transistors. Next, we present an accurate estimation and modeling of total chip leakage considering both inter- and intra-die process variations. Finally, we explore the effectiveness of dual-Vt design under aggressive scaling of technology. The present way of realizing high-Vt devices results in high junction tunneling leakage compared to low-Vt devices, which in turn may result in negligible leakage savings for dual- Vt designs. Moreover, increase in process variation severely affects the yield of such designs. This work suggests important measures and different design options that need to be incorporated in conventional dual- Vt design to achieve total leakage power improvement while ensuring yield.




Roy, Purdue University.

Subject Area

Electrical engineering

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