Microarchitectural techniques for power-related issues in scaled technologies

Michael D Powell, Purdue University

Abstract

Downscaling in CMOS technologies results in more devices, faster transistors, and lower supply voltages in microprocessors. While enabling high performance, this trend creates power-related challenges including chip power, reduced noise margins, heat, and energy and latency in long wires. Though traditionally addressed at the circuit level, scaling trends necessitate microarchitectural solutions for these challenges. This dissertation focuses on architectural solutions for two of these problems: the inductive-noise problem caused by small noise margins and the power-density problem caused by hot spots in processors. Inductive noise is a reliability issue caused by current variations (di/dt) which are converted to supply-voltage glitches by impedances in the power-supply network. Historically, inductive noise was addressed using decoupling capacitors to maintain low power supply impedance over a wide range of frequencies. However, even well-designed power supplies exhibit a few high-impedance peaks, most importantly at medium (around 50–200 MHz) and high (near the clock) resonant frequencies. To address medium-frequency noise, I propose two architectural techniques. The first, pipeline damping, controls instruction issue to shrink the magnitude of current variations at the resonant frequency. The second, resonance tuning, moves the frequency of current variations away from the resonant frequency, thus reducing supply noise. To address high-frequency noise, I propose pipeline muffling and a-priori current ramping, which control high-frequency variations in resource usage, reducing the need for decoupling capacitors. The power-density problem worsens with technology generations as scaling of current, clock speed, and device density outpaces the downscaling of supply voltage and thermal ability of packages to dissipate heat. Power density is characterized by localized chip hot spots that can reach critical temperatures and cause failure. Previous architectural approaches to power density target superscalar processors. Future processors, however, are likely to be chip multiprocessors (CMPs) with simultaneously-multithreaded (SMT) cores which pose unique challenges and opportunities for power density. I propose heat-and-run SMT thread assignment to increase processor-resource utilization before cooling becomes necessary by co-scheduling threads that use complementary resources. I propose heat-and-run CMP thread migration to migrate threads away from overheated cores, leveraging availability of contexts on alternate cores to maintain throughput while allowing overheated cores to cool.

Degree

Ph.D.

Advisors

Vijaykumar, Purdue University.

Subject Area

Electrical engineering|Computer science

COinS