4H-SiC power DMOSFETs
This thesis focuses on the design, fabrication, and characterization of power DMOSFETs in 4H-SiC material. 4H-SiC has a wide bandgap (Eg = 3.23 eV), a high breakdown electric field (2.2 MV/cm), and a high electron mobility (μnbulk∥C = 900 cm2/Vsec, μnbulk⊥C = 800 cm2/Vsec) which makes it very suitable for high-voltage, high-temperature power device applications. Conventional 4H-SiC DMOSFETs (D-doubly implanted) suffer from high specific-on resistances. This is because the activation of the p-type base implantation requires a high temperature (1700°C) annealing step which creates surface roughness. As a result, the inversion channel mobility is drastically reduced. In order to alleviate the surface roughness phenomenon, two new structures, namely the “etched epitaxial base DMOSFET (epiDMOS and epiAFET),” and the “implanted epitaxial base DMOSFET” are proposed. These structures do not require any p-type implants and take advantage of the epitaxial p-type base doping. The blocking voltage, critical electric fields, and on-resistance were studied with MEDICI simulations. We have demonstrated the fabrication of the first 4H-SiC epiDMOSFET structures with a patterned p+ base layer, a p-type channel layer, and a phosphorus source implant. The advantage of this is to keep the overall processing temperatures below 1200°C. Unfortunately, these devices were limited by high on-resistances. In addition, an unknown source of base leakage current was observed in the off-state. The requirement of the p-type channel region over the patterned p+ base led to a “tapered epilayer” problem which resulted in the discontinuity of the channel. The n-type plug region necessary to provide a conduction path from the channel to the drain was identified as a source of additional resistance in series with the channel and drain. The “implanted epitaxial base” structure does not require any p-epitaxial layer patterning and is much simpler to process. From design study and MEDICI simulations, we find that the epitaxial base structures requiring the n-type plug implant requires a high cell pitch since we have to allow lengths for realistic fabrication processes. ^ Finally, we demonstrate the first short-channel, counter-doped, self-aligned 4HSiC DMOSFETs. Ongoing studies on 4H-SiC MOS structures show significant improvements to inversion channel mobility by activating the p-type implants in a silane ambient which minimizes the step-bunching phenomenon. (Abstract shortened by UMI.) ^
Major Professor: James A. Cooper, Purdue University.
Engineering, Electronics and Electrical
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