A digital architecture for phased array radar
Digital phased arrays provide substantial improvements over their analog, mechanical counterparts. The added degrees of freedom provided by per-element digital control enables expansion on radar function and performance but imposes heavy requirements on digital processing. The demand for digital processing continues to grow as improvements in conversion technology between analog and digital provides wider bandwidths with higher dynamic ranges and multifunction phased arrays become more desirable. This processing need is commonly met with expensive, high throughput architectures that trade off scalability for functionality due to current technology limitations and/or restrictions imposed by the architecture itself. This thesis proposes a link between traditional radar concepts and computer networking methodology, introducing a method to enable scalability for planar array configurations of narrow bandwidths while meeting data processing requirements for a functioning radar. This design is a hybrid of hierarchical beamforming with computer networking practices that capitalizes on the flexibility of data packetization. Additionally, this design coalesces necessary radar hardware into a single unit architecture, comprised of commodity technology, that further aids scalability. Simulation of the communication network, packetization structure, and processing system shows that the proposed method will meet the requirements of traditional radar if realized as a physical system.^
Vijay S. Pai, Purdue University, William J. Chappell, Purdue University.
Engineering, Computer|Engineering, Electronics and Electrical
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