A 500MHz to 6GHz software-defined receiver in 130nm CMOS using the mixer switching method
Abstract
In this work, a low-power, low-noise, high-linearity software-defined receiver is presented that selects whether or not to skip the G m stage in the receiver path. The full frequency range of the receiver is 500MHz to 6GHz. The design takes advantage of the differences between a common-gate and a TIA output stage to boost linearity. As a final measure, the LNA has a low-gain mode to be used when selectivity is not an issue. For each block of the design, a circuit and noise analysis is performed and simple equations are found governing the behavior of the basic blocks. Also, for each block, simulation are performed and analyzed to verify performance. The full receiver achieves <4dB NF in high gain mode and greater than>-9dBm IIP3 in low gain mode while still boasting a NF <6.5dB over the entire bandwidth, while only requiring 23mW in its highest current drawing state.
Degree
M.S.E.C.E.
Advisors
Jung, Purdue University.
Subject Area
Electrical engineering
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