Experimentally Validated Quantum Transport Models for Tunneling Devices Based on Novel Materials
The desire to reduce the power consumption of consumer electronics has driven the semiconductor industry to seek smaller transistors and to operate them at lower supply voltages. A reduction in the transistor’s dimensions by a certain fraction can reduce the power consumption by the same amount, for a specific operation speed. The semiconductor industry employs a 14nm feature size for its latest technology node and is pushing it down to 10nm. Moreover, reducing the supply voltage can also significantly lower the power consumption. However, the limit on the supply voltage is set by the threshold voltage, which is more than 0.6V given the fundamental limit of 60mV/dec for MOSFETs. Further reduction in supply voltage and consequently power consumption can be achieved with tunneling transistors that can overcome this limit. Tunneling transistors, however, face challenges with low ON current leading to slow performance. The ON current can be boosted by reducing the tunneling distance, either with a tight gate control in 2D materials or with internal piezo-polarization in nitrides. An accurate prediction of the performance of such nanoscale tunneling devices is obtained from experimentally validated quantum transport simulations. Two practical aspects have been added for a realistic prediction; incomplete ionization of doping and scattering effects on confined states in hetero-structures. Such additions have led to better agreements with relevant experimental measurements. The models have been employed to propose likely candidates towards future low power tunneling transistors based on novel materials and designs.
Klimeck, Purdue University.
Electrical engineering|Nanotechnology|Computer Engineering
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