Atomic Layer Epitaxy Dielectric Based GaN MOS Devices and Beyond

Hong Zhou, Purdue University


GaN HEMT usually suffers from high Ig and ID current collapse due to its limited Schottky barrier height and high density of surface states. Although GaN MOSHEMT with amorphous gate dielectric is an effective way to suppress the Ig and passivate the surface states, high-quality gate dielectric on GaN MOS devices are still lacking. In this work, single crystalline gate dielectric Mg0.25Ca0.75O, grown by ALE, has been successfully integrated into three kinds of GaN MOSHEMTs, namely InAlN/GaN/SiC, AlGaN/GaN/SiC and AlGaN/GaN/Si MOSHEMTs. With a nearly lattice-matched oxide, the interface quality between the oxide and barrier is significantly improved. Ig is reduced by several orders of magnitudes compared to HEMTs. All three kinds of MOSHEMTs exhibit high ID on/off ratio exceeding 1011, near ideal SS, negligible ID-V GS hysteresis and negligible current collapse. RF small-signal characteristics of AlGaN/GaN/SiC MOSHEMTs show ft/fmax of 101/150 GHz for a Lg of 120 nm device and large-signal characteristics with Pout of 4.18 W/mm for a Lg=150 nm device at f=35 GHz. Enhancement-mode non-recessed AlGaN/GaN/Si fin-MOSHEMTs are also realized through the side-wall depletion of the fin structures. Combining with the high ID, high peak gm, and low Ron, MgCaO turns out to be a new and very promising gate dielectric for GaN MOS technology. Beyond the wide bandgap semiconductor GaN, promising next generation ultra-wide bandgap semiconductor β-Ga2O3 is also investigated. Piranha solution and PDA were first used to optimize the ALD Al2O3/β-Ga2O3 interface. Low C-V hysteresis of 0.1 V and Dit=2.3×1011 cm–2˙eV–1 are achieved due to the passivated dangling bonds at the interface. Meanwhile, we have demonstrated a record high ID of 600/450 mA/mm for D/E-mode back-gate GOOI FETs at a β-Ga2O3 doping concentration of 2.8×1018 cm–3. Following the motivation of chasing higher I D and lower Ron, we have increased the doping concentration to 7.8×1018 cm–3 and the record ID has been improved to 1.5/1.0 A/mm for D/E-mode GOOI FETs at a lower Ron and Rc. All our GOOI FETs based on atomically flat ?-Ga2O3 nano-membrane has a RMS of 0.3 nm, high on/off ratio of 1010, and low SS of 140~160, even with 300 nm SiO2 gate dielectric. Finally, we have evaluated the self-heating effect and thermal property of top-gate GOOI FETs on SiO2/Si and sapphire substrates. Through utilizing a higher thermal conductivity sapphire substrate, the device only has a temperature increase of 43 °C even at a high device operation P=0.91 kW/mm2. High quality interface, high ID and on/off ratio, near ideal SS of 63 mV/dec, and reduced self-heating effect on sapphire substrate, top-gate GOOI FET shows the great promise as next generation high power devices.




Ye, Purdue University.

Subject Area

Electrical engineering|Materials science

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