Design, compact modeling and characterization of nanoscale devices
Electronic device modeling is a crucial step in the advancement of modern nanotechnology and is gaining more and more interest. Nanoscale complementary metal oxide semiconductor (CMOS) transistors, being the backbone of the electronic industry, are pushed to below 10 nm dimensions using novel manufacturing techniques including extreme lithography. As their dimensions are pushed into such unprecedented limits, their behavior is still captured using models that are decades old. Among many other proposed nanoscale devices, silicon vacuum electron devices are regaining attention due to their presumed advantages in operating at very high power, high speed and under harsh environment, where CMOS cannot compete. Another type of devices that have the potential to complement CMOS transistors are nano-electromechanical systems (NEMS), with potential applications in filters, stable frequency sources, non-volatile memories and reconfigurable and neuromorphic electronics. In this work, a compact scalable nonlinear RF MOSFET model for NMOS transistors in a standard 45nm CMOS SOI technology is presented. This model employs a simple nonlinear core known as the Virtual Source (VS) model and adds parasitic elements around it to accurately simulate the RF performance of NMOS transistors up to 40GHz. The traditional long-channel thermal noise model is replaced by a combined shot-thermal noise model for the first time to accurately predict the noise behavior of these short-channel transistors up to 40GHz. The model parameters are extracted from DC, S-parameter and noise measurements across different bias conditions and for different device dimensions to achieve a scalable nonlinear model. In addition to CMOS modeling, silicon nanowire field emitter arrays, which yield large current densities with high reliability and low turn-on voltages are designed, and implemented. An electro-thermal simulation is performed to obtain the parameters that optimize the device performance. The silicon emitter arrays are fabricated using a self-assembled technique for the first time. Silicon nanowire FEAs fabricated with this technique are dense (∼75% fill factor), highly repeatable and reproducible, and low-cost. An ungated two-terminal device and a gated vacuum transistor are fabricated in this technology and are characterized. Various CMOS integrated NEMS resonators are fabricated and characterized. A compact model for double-clamped CMOS Silicon on Insulator (SOI) NEMS devices is constructed and implemented. The model covers both linear and nonlinear characteristics of nanoscale single gated and double gated resonators made of silicon beam of different sizes and gaps. This model can also capture the hardening or softening effects, Duffing-type response and hysteresis responses, that are observed in such devices.
Mohammadi, Purdue University.
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