Electron Scattering in Quasi-one-dimensional Nanoscale Transistors

SungGeun Kim, Purdue University


As the sizes of silicon metal-oxide-semiconductor field effect transistors (MOSFET) are scaled down to a nano-meter regime, conventional planar structures are subject to short channel effects. Their subthreshold characteristic is so degraded that a new device structure or material is indispensable to further reduce device dimensions properly. Silicon-on-insulator or double-gate structure is not enough to scale the device dimensions below the channel length of 5 nm. Quasi-one-dimensional structures such as silicon nanowire transistors and graphene nanoribbon transistors may be a solution for ultimate scaling limit. These transistors are numerically explored extensively through atomistic quantum transport simulations based on a tight-binding model. The main focus of this work is to analyze performance metrics of these one dimensional transistors especially when scattering mechanisms such as interface (edge) roughness scattering, electron-phonon scattering, and/or impurity scattering are included. Experimental data are studied and compared with simulation data to provide insights and to explore the device design in ultimate scaling limit. It is found that for high performance logic applications, silicon nanowire transistors show similar performance as graphene nanoribbon transistors. For low power logic applications, graphene nanoribbon tunneling transistors show a great potential in reducing power consumption if cleverly designed.




Klimeck, Purdue University.

Subject Area

Electrical engineering|Nanotechnology|Computer science

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