Fine-grained energy and thermal management using real-time power sensors
With extensive use of battery powered devices such as smartphones, laptops and tablets energy efficiency has become a critical design criterion in today’s System on Chip (SoC) designs. Although shrinking device sizes helped to lower production costs and enabled faster computing, they also resulted in continued rise in power densities. As a result, significant new challenges have appeared in system reliability (due to thermal failures) and feasibility (due to cooling costs). Techniques such as Dynamic Voltage and Frequency Scaling (DVFS), activity migration, power gating, clock gating and fetch toggling have been proposed to reduce power densities and increase energy efficiency. Such techniques require real-time information such as workload, temperature, power etc. for which thermal sensors and hardware performance counters are deployed. However, temperature sensors have slow response times and cannot reliably predict future workloads without resorting to computationally intensive algorithms. Hardware performance counters on the other hand, are only proxy measures of dynamic power and cannot account for static power and variations in ambient conditions. In this dissertation, novel sensors for concurrent and fast estimation of power and temperature, with simple calibration schemes for improved accuracy have been proposed. Occupying less than 0.01mm2 on-chip area, these sensors consume less than 200μW and provide fast response within 100ns, which is a significant advancement of state-of-the-art in sensors. This sensors is then deployed in multi-core environments employing DVFS and activity migration to evaluate, and quantify their performance vis-a-vis Hardware Performance counters and temperature sensors.
Jung, Purdue University.
Computer Engineering|Electrical engineering
Off-Campus Purdue Users:
To access this dissertation, please log in to our