High-heat-flux removal is critical for the nextgeneration electronic devices to reliably operate within their temperature limits. A large portion of the thermal resistance in a traditional chip package is caused by thermal resistances at interfaces between the device, heat spreaders, and the heat sink; embedding the heat sink directly into the heat-generating device can eliminate these interface resistances and drastically reduce the overall thermal resistance. Microfluidic cooling within the embedded heat sink improves the heat dissipation, with two-phase operation offering the potential for dissipation of very high heat fluxes while maintaining moderate chip temperatures. To enable multichip stacking and other heterogeneous packaging approaches, it is important to densely integrate all fluid flow paths into the device; volumetric heat dissipation emerges as a performance metric in this new heat sinking paradigm. In this paper, a compact hierarchical manifold microchannel design is presented that utilizes an integrated multilevel manifold distributor to feed coolant to an array of microchannel heat sinks. The flow features in the manifold layers and microchannels are fabricated in silicon wafers using deep reactive-ion etching. The heat source is simulated via Joule heating using thin-film platinum heaters. The on-chip spatial temperature measurements are made using four-wire resistance temperature detectors. The individual manifold layers and the microchannel-bearing wafers are diced and bonded into a sealed stack via thermocompression bonding using gold layers at the mating surfaces. Thermal and hydrodynamic testing is performed by pumping the dielectric fluid HFE-7100 through the device at a known flow rate,


Microchannel heat sink, microfluidics, microheater, resistance temperature detector (RTD), volumetric heat density.

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M. Chakraborty, J.A. Weibel, J.A. Schaber, and S.V. Garimella, The wetting state of water on a rose petal, Advanced Materials Interfaces, Vol. 6, 1900652, 2019.