Performance Projections for Ballistic Carbon Nanotube Field-effect Transistors

The performance limits of carbon nanotube field-effect transistors ͑CNTFETs͒ are examined theoretically by extending a one-dimensional treatment used for silicon metal–oxide– semiconductor field-effect transistors ͑MOSFETs͒. Compared to ballistic MOSFETs, ballistic CNTFETs show similar I – V characteristics but the channel conductance is quantized. For low-voltage, digital applications, the CNTFET with a planar gate geometry provides an on-current that is comparable to that expected for a ballistic MOSFET. Significantly better performance, however, could be achieved with high gate capacitance structures. Because the computed performance limits greatly exceed the performance of recently reported CNTFETs, there is considerable opportunity for progress in device performance. Recent demonstrations of carbon nanotube field-effect transistors and circuits suggest that these devices could play an important role in future electronic systems. 1– 4 Previous theoretical studies of nanotube devices have mostly focused on two terminal devices, such as PN junctions and Schottky diodes, 5–7 but from an application point of view, the transistor is the most interesting. To date, experimentally fabricated carbon nanotube field-effect transistors ͑CNTFETs͒ have employed channel lengths of several hundred or thousand na-nometers and often display a large contact resistance between metal and nanotube. In addition, it is not yet clear how these devices operate. One possibility is that the gate field modulated the width of a barrier at the source contact, analogous to the Schottky barrier metal–oxide–semiconductor field-effect transistor ͑MOSFET͒. 8 In this letter, we theoretically evaluated the performance limit for CNTFETs by extending the one-dimensional ͑1D͒ theory of ballistic MOSFETs to ideal, ballistic CNTFETs. We show that the characteristics of ballistic CNTFETs are affected by the 1D nature and nonparabolic band structure of the nanotube. The results indicate that reported CNTFETs operate well below the upper limit and suggest that improved technology ͑e.g., low resistance contacts, better gate electrostatics, and shorter channel lengths͒ will produce substantial performance improvements. Finally, we compare ideal, ballistic CNTFETs to ideal, ballistic MOSFETs in order to examine the role for CNTFETs in low-voltage, high-density, digital applications. The modeled device, a coaxially gated, N-type CNTFET with nanotube diameter dϭ1 nm, insulator thickness t ins ϭ1 nm, and dielectric constant ␬ϭ4, is schematically shown in Figs. 1͑a͒ and 1͑b͒. The intrinsic nanotube channel is separated from the source/drain metal contact by the heavily N-doped nanotube source/drain extension to minimize the Miller capacitance between gate and source/drain electrode. The source/drain region could also be realized by using weakly coupled metal-nanotube contacts …


Performance projections for ballistic carbon nanotube field-effect transistors
Jing Guo, a) Mark Lundstrom, and Supriyo Datta The performance limits of carbon nanotube field-effect transistors ͑CNTFETs͒ are examined theoretically by extending a one-dimensional treatment used for silicon metal-oxidesemiconductor field-effect transistors ͑MOSFETs͒.Compared to ballistic MOSFETs, ballistic CNTFETs show similar I -V characteristics but the channel conductance is quantized.For low-voltage, digital applications, the CNTFET with a planar gate geometry provides an on-current that is comparable to that expected for a ballistic MOSFET.Significantly better performance, however, could be achieved with high gate capacitance structures.Because the computed performance limits greatly exceed the performance of recently reported CNTFETs, there is considerable opportunity for progress in device performance.© 2002 American Institute of Physics.͓DOI: 10.1063/1.1474604͔2][3][4] Previous theoretical studies of nanotube devices have mostly focused on two terminal devices, such as PN junctions and Schottky diodes, [5][6][7] but from an application point of view, the transistor is the most interesting.To date, experimentally fabricated carbon nanotube field-effect transistors ͑CNTFETs͒ have employed channel lengths of several hundred or thousand nanometers and often display a large contact resistance between metal and nanotube.In addition, it is not yet clear how these devices operate.One possibility is that the gate field modulated the width of a barrier at the source contact, analogous to the Schottky barrier metal-oxide-semiconductor field-effect transistor ͑MOSFET͒. 8In this letter, we theoretically evaluated the performance limit for CNTFETs by extending the one-dimensional ͑1D͒ theory of ballistic MOSFETs to ideal, ballistic CNTFETs.We show that the characteristics of ballistic CNTFETs are affected by the 1D nature and nonparabolic band structure of the nanotube.The results indicate that reported CNTFETs operate well below the upper limit and suggest that improved technology ͑e.g., low resistance contacts, better gate electrostatics, and shorter channel lengths͒ will produce substantial performance improvements.Finally, we compare ideal, ballistic CNTFETs to ideal, ballistic MOSFETs in order to examine the role for CNTFETs in low-voltage, high-density, digital applications.
The modeled device, a coaxially gated, N-type CNTFET with nanotube diameter dϭ1 nm, insulator thickness t ins ϭ1 nm, and dielectric constant ϭ4, is schematically shown in Figs.1͑a͒ and 1͑b͒.The intrinsic nanotube channel is separated from the source/drain metal contact by the heavily N-doped nanotube source/drain extension to minimize the Miller capacitance between gate and source/drain electrode.The source/drain region could also be realized by using weakly coupled metal-nanotube contacts with an appropriate metal work function. 9We assume that the metal-nanotube contact resistance, R C ϭ0, and carrier transport through nanotube is ballistic ͑no scattering͒.Calculations base on these assumptions should establish the upper limit of CNTFET performance.
1][12][13] The procedure begins by calculating the equilibrium charge density, Q L , versus gate voltage, V G , by solving the Poisson equation selfconsistently with the carrier population in the carbon nanotube. 14,15Above the threshold voltage, V T , the charge in the nanotube increase approximately linearly with the gate voltage.In a long-channel transistor, the charge density at the a͒ Electronic mail:guoj@purdue.edubeginning of the channel, Q L , is equal to its value at equilibrium and is independent of the drain voltage.In an electrostatically well-designed, short-channel transistor, Q L is approximately independent of drain voltage, except that the value of V T may be shifted by two-dimensional electrostatics. 15We may, therefore, assume that an appropriately shifted, equilibrium Q L vs V G relation holds at the top of the source-channel barrier.The magnitude of the resulting V T is selected to achieve the specified I off .This approach captures the essential physics of the device, but a two-or three-dimensional solution of Poisson's equation will be necessary to evaluate the magnitude of the V T shift and the output conductance, and to address the scaling limit for CNTFETs. 16t the top of the barrier, the ϩk states are populated by injection from the source and the Ϫk states by injection from the drain, as shown in Fig. 1͑c͒.Therefore, the electron density for the ith conduction band is where s is the source Fermi level and, f (E) is the Fermi function, and the density of states is 17 where bϷ1.44 Å and tϷ2.5 eV are the C-C bonding distance and energy, respectively, and ⌰(x) equals 1 for positive x and 0 otherwise.The parameter, E 0 , is the middle gap energy, and ⌬ i is the bottom of the ith conduction band relative to E 0 . 17Summation of electron densities over all conduction bands gives the total electron density.If we set the source Fermi level to zero, then the only unknown in the above expressions is E 0 .Its value is adjusted iteratively to maintain the previously computed, shifted equilibrium charge density, Q L (V G ). Finally, having determined E 0 , the currents in the positive and negative half k states are evaluated by integration over energy, and their difference gives the drain current.The details of this procedure and its validation by detailed simulations are discussed by Natori 10,11 and Lundstrom. 16igure 2 shows I -V characteristics of the ballistic, coaxially gated CNTFET assuming a power supply voltage of 0.4 V, which is appropriate for high density, digital applications in the future. 18The left axis of Fig. 2͑a͒ shows the computed log(I D ) vs V G .As noted earlier, the value of the threshold voltage was selected ͑by adjusting the gate electrode work function͒ to produce 10 Ϫ2 A of off-current.͑The off-current specified for 2016 node of ITRS, I off ϭ10 A/m, 18 times the nanotube diameter, dϭ1 nm.͒The on-current is 11.2 A, well-below the 25 A obtained for metallic nanotubes 19 because of the limited amount of charge that can be induced with a low power supply voltage and the modest dielectric constant assumed.Comparisons with conventional, planar MOSFETs are difficult because of the difference in device geometries, but we note that the on-off current ratio (I on /I off Ϸ1120) outperforms that of a 10 nm ballistic MOSFET with the same insulator and power supply (I on /I off Ϸ110).
The right axis of Fig. 2͑a͒ shows that the transconductance of the coaxially gated CNTFET at V G ϭ0.4 V is 63 S, about two orders of magnitude larger than the value reported in a recent study 2 ͑ϳ0.342S͒ due to two reasons.First, our use of coaxial geometry with thin insulator offers better gate controlled electrostatics and about an order of magnitude larger C G than the planar geometry with thick gate insulator used in Ref. 2. Second, the average carrier velocity at the top of the barrier (ϳ2.7ϫ10 7 cm/s) of the ideal, ballistic CNTFET is larger than the value (ϳ6ϫ10 5 cm/s) in the experimental CNTFET, which has a channel length of about 1 m and is likely to be affected by scattering.The larger g m of the ballistic, coaxial CNTFET suggests that better electrostatic design and downscaling the device, would allow it to operate closer to the ballistic limit and substantially improve its performance.
The drain current saturation displayed in the output characteristics ͓Fig.2͑b͔͒ occurs ͑as for a ballistic MOSFET͒ when the drain bias is large, so that negative k-states at the top of the barrier are not occupied.The inset in Fig. 2͑b͒ shows, however, that the low-bias channel conductance, G CH , versus gate voltage behaves differently than that of a MOSFET.For a MOSFET in the degenerate limit, G CH ϭM (2e 2 /h), where M is the number of occupied transverse modes. 20Because the width of a MOSFET is typically large, the number of transverse modes, and therefore G CH , increases continuously with gate voltage.For the CNTFET, however, the channel conductance versus gate voltage is quantized in units of G 0 ϭ4e 2 /h, because only two modes per subband can propagate.͑This effect has been discussed by Yamada. 21͒ The transition between conductance steps is broadened at room temperature such that for low voltage operation, the channel conductance is approximately proportional to gate voltage.Because the charge at the beginning of the channel is determined by metal-insulator-semiconductor electrostatics, it is useful to express the on-current as the product of charge times the injection velocity ͓ inj ϵI on /Q L (0)͔, which is simply the average carrier velocity at the top of the barrier.Figure 3 plots the injection velocity ͑on the left axis͒ and the percentage of charge in the first subband ͑on the right axis͒ versus gate voltage at V D ϭ1.0 V.Under low gate voltages (V G Ͻ0.8 V), the relatively small amount of charge at the top of the barrier occupies only the first subband.As the gate voltage increases from V G ϭ0 V, the Fermi level, E F , moves to a steeper part of the band, and the injection velocity increases rapidly until E F hits the bottom of the second subband.The band structure of a carbon nanotube allows higher injection velocities than that for silicon MOSFETs, but only at high gate voltages for which the Fermi level is well above the bottom of the first subband.
Finally, we compare the idealized, ballistic CNTFET to an idealized, ballistic single-gate silicon MOSFET with the same gate insulator thickness and dielectric constant.This comparison is most readily done for the planar nanotube array.We assume the nanotube diameter dϭ1 nm, insulator thickness t ins ϭ1 nm, dielectric constant ϭ4, and spacing between neighboring nanotube Sϭ2d. 2 ͑Reducing the spacing to Sϭd does not double the device performance because each nanotube image to a narrower width on the gate plane. 14͒ The gate work functions of the planar CNTFET and MOSFET are adjusted to produce I off ϭ10 A/m. 10 The resulting ballistic on-current of the planar CNTFET at V DD ϭ0.4 V, 790 A/m, is less than that for the silicon MOSFET, 1100 A/m.The difference occurs for two reasons.First, when the gate oxide is thin, an array of cylindrical nanotubes ͑with charge almost uniformly distributed around nanotubes because most of the charge occupies the first subband͒ is not as effective as the planar silicon MOS capacitor in gating charge into the nanotube array. 14Second, although the nanotube band structure allow a upper limit of inj Ϸ8ϫ10 7 cm/s ͑carrier velocity in graphene͒, at V G ϭ0.4 V the limited amount of charge only occupies the bottom of the first subband and results in inj Ϸ1.8ϫ10 7 cm/s.The performance of the CNTFET, with respect to silicon MOSFETs, may be improved with better gate electrostatics.For example, insulators applicable to CNTFETs ͑e.g., Al 2 O 3 , dielectric constant of 9.4͒ can have higher dielectric constant than SiO 2 and imbedding the nanotube in the gate insulator may increase C G somewhat. 4 Such changes im-prove the gate capacitance and result in comparable ballistic on-current to silicon MOSFETs.Even more effective electrostatic gating may allow the CNTFET to outperform the MOSFET.For example, the coaxially gated CNTFET delivers an on-current ͑11.2 A͒ that much higher than the oncurrent per nanotube for the planar array ͑1.6 A͒.The use of a higher dielectric constant would also benefit the CNT-FET, and if high gate voltages can be used, the ballistic currents should be substantially greater than that of a corresponding MOSFET because both the injection charge density and velocity increase.In summary, the ballistic limit performance of CNTFETs was evaluated.The I -V characteristics are similar to those of a conventional MOSFET, except for the occurrence of a quantized channel conductance.The on-current and transconductance of the computed ballistic CNTFET are well above the values currently being obtained experimentally ͑due to our assumption of ideal metal-nanotube contacts, ballistic channel transport, and better gate controlled electrostat-ics͒, suggesting possibility to improve the performance substantially by better device design.For low voltage operation, the ballistic CNTFET with a planar gate geometry shows no advantage over the ballistic silicon MOSFET in terms of on-current, significantly better performance, however, is achieved with a coaxially gated geometry.

FIG. 1 .
FIG. 1. Schematic diagrams of the modeled, coaxially gated CNTFET.͑a͒ Cross section along the nanotube channel direction.The hatched line regions are the heavily N-doped nanotube source and drain, and the thin crosshatched line region is the intrinsic nanotube channel.͑b͒ Cross section perpendicular to the nanotube channel direction, which shows the gate configuration.͑c͒ The subband profile vs the position along the channel direction.At the top of barrier, the ϩk states and the Ϫk states are populated according to the source Fermi level s and the drain Fermi level D , respectively.

FIG. 2 .
FIG. 2. I -V characteristics of the coaxially gated CNTFET.͑a͒ Computed log(I D ) vs V G ͑on the left axis͒ and transconductance vs V G ͑on the right axis͒ at V D ϭ0.4 V. ͑b͒ The computed I D vs V D characteristic with gate bias as a parameter.͑V G ϭ0.1-0.4V, 0.1 V/step.͒The inset shows the quantized channel conductance vs gate voltage at Tϭ300 K.The normalization conductance G 0 ϭ4e 2 /h, where e is the electron charge and h the Planck constant.
This work was supported by the National Science Foundation, Grant No. EEC-0085516.Helpful discussions with P. McEuen, through the MARCO/DARPA Focused Research Center on Materials, Structures and Devices, are acknowledged.