Metal–insulator–semiconductor Electrostatics of Carbon Nanotubes

Carbon nanotube metal–insulator–semiconductor capacitors are examined theoretically. For the densely packed array of nanotubes on a planar insulator, the capacitance per tube is reduced due to the screening of the charge on the gate plane by the neighboring nanotubes. In contrast to the silicon metal–oxide–semiconductor capacitors, the calculated C – V curves reflect the local peaks of the one-dimensional density-of-states in the nanotube. This effect provides the possibility to use C – V measurements to diagnose the electronic structures of nanotubes. Results of the electrostatic calculations can also be applied to estimate the upper-limit on-current of carbon nanotube field-effect transistors. The carbon nanotube field-effect transistor ͑CNTFET͒ 1–3 is a promising candidate for future electron devices. Rapid progress in the field has recently made it possible to fabricate digital and analogue CNTFET-bases circuits, such as logic gates, static memory cells, and ring oscillators. 4,5 To explore the role of CNTFETs in future integrated circuits, it is important to evaluate their performance as compared to the metal–oxide–semiconductor field-effect transistor ͑MOSFET͒. 3 A transistor's on-current, an important performance metric, is the product of the charge induced by the gate and the average carrier velocity, 6 so the first step is to understand the gate-controlled electrostatics of a carbon nanotube metal–insulator–semiconductor ͑MIS͒ capacitor. Theoretical studies of carbon nanotube electrostatics have focused on two-terminal devices and the electrostatics along the nanotube direction. 7,8 The planar gate-controlled electrostatics has been treated approximately in experimental studies in order to qualitatively explain or fit measured data. 5,9 In this letter, the MIS electrostatics of carbon nano-tube capacitors in three different geometries is analyzed by solving the two-dimensional Poisson equation self-consistently with carrier statistics of nanotubes. The results show that for the densely packed array of nanotubes on a planar insulator, the capacitance per tube is reduced due to the screening of the charge on the gate plane by the neighboring nanotubes. In contrast to silicon, planar MOS capaci-tors, the capacitance is strongly influenced by the nanotube's one-dimensional density-of-states. The results also show that careful electrostatic design will be critical for the performance of CNTFETs. The three nanotube capacitors examined in this study, each with a semiconducting nanotube having a diameter of Dϭ1 nm, are shown in Fig. 1. In the third dimension ͑out of the page͒ the nanotube is assumed to be connected to ground, which supplies the carriers to balance the charge on the gate. For comparison …


Metal-insulator-semiconductor electrostatics of carbon nanotubes
Jing Guo, a) Sebastien Goasguen, Mark Lundstrom, and Supriyo Datta 1285 Electrical Engineering Building, Purdue University, West Lafayette, Indiana 47907 ͑Received 14 January 2002; accepted for publication 28 June 2002͒ Carbon nanotube metal-insulator-semiconductor capacitors are examined theoretically.For the densely packed array of nanotubes on a planar insulator, the capacitance per tube is reduced due to the screening of the charge on the gate plane by the neighboring nanotubes.In contrast to the silicon metal-oxide-semiconductor capacitors, the calculated C -V curves reflect the local peaks of the one-dimensional density-of-states in the nanotube.This effect provides the possibility to use C -V measurements to diagnose the electronic structures of nanotubes.Results of the electrostatic calculations can also be applied to estimate the upper-limit on-current of carbon nanotube field-effect transistors.© 2002 American Institute of Physics.͓DOI: 10.1063/1.1502188͔ The carbon nanotube field-effect transistor ͑CNTFET͒ [1][2][3] is a promising candidate for future electron devices.Rapid progress in the field has recently made it possible to fabricate digital and analogue CNTFET-bases circuits, such as logic gates, static memory cells, and ring oscillators. 4,5To explore the role of CNTFETs in future integrated circuits, it is important to evaluate their performance as compared to the metal-oxide-semiconductor field-effect transistor ͑MOSFET͒. 3A transistor's on-current, an important performance metric, is the product of the charge induced by the gate and the average carrier velocity, 6 so the first step is to understand the gate-controlled electrostatics of a carbon nanotube metal-insulator-semiconductor ͑MIS͒ capacitor.
Theoretical studies of carbon nanotube electrostatics have focused on two-terminal devices and the electrostatics along the nanotube direction. 7,8The planar gate-controlled electrostatics has been treated approximately in experimental studies in order to qualitatively explain or fit measured data. 5,9In this letter, the MIS electrostatics of carbon nanotube capacitors in three different geometries is analyzed by solving the two-dimensional Poisson equation selfconsistently with carrier statistics of nanotubes.The results show that for the densely packed array of nanotubes on a planar insulator, the capacitance per tube is reduced due to the screening of the charge on the gate plane by the neighboring nanotubes.In contrast to silicon, planar MOS capacitors, the capacitance is strongly influenced by the nanotube's one-dimensional density-of-states.The results also show that careful electrostatic design will be critical for the performance of CNTFETs.
The three nanotube capacitors examined in this study, each with a semiconducting nanotube having a diameter of Dϭ1 nm, are shown in Fig. 1.In the third dimension ͑out of the page͒ the nanotube is assumed to be connected to ground, which supplies the carriers to balance the charge on the gate.For comparison to a silicon MOS capacitor, we assume a silicon doping of N A ϭ10 18 cm Ϫ3 , insulator thickness t ins ϭ1 nm and a dielectric constant of ins ϭ4.It is important that results be compared at the same gate overdrive, (V G ϪV T ), so the gate work functions were selected to produce the same threshold voltage V T for the CNT and MOS capacitors.
The nanotube capacitance versus gate voltage is computed as follows.For an assumed potential of the nanotube, the charge density, Q L , was obtained from

͑1͒
where e is the electron charge, sgn(E) is the sign function, D(E) is the density-of-states ͑DOS͒ of the nanotube 10 and E ˜FϭeV CNT is the position of Fermi level relative to the middle of the energy gap ͑we assume an intrinsic nanotube͒, and V CNT is the average potential of the nanotube.We adopt a semiclassical approach in which the effect of gate voltage is to move the subbands of the nanotube rigidly up and down without changing the D(E), the nanotube DOS.This assumption is valid for the coaxial geometry because the cylindrical symmetry produces the same potential for each carbon atom.But for a planar geometry, potential drops across the nanotube can perturb its band structure. 11As long as the potential variation across a ϳ1 nm diameter nanotube is below 0.8 V, the effect is small, 11 so our use of a 0.4 V power supply, as required for high-density digital systems, 12 suggests that band structure perturbations will be small in this case.a͒ Electronic mail: guoj@purdue.eduHaving computed the charge in the nanotube for an assumed nanotube potential, the corresponding gate voltage is

͑2͒
where C ins is the gate to nanotube insulator capacitance ͑a constant independent of gate voltage͒, V G is the gate voltage, and V fb the flatband voltage as determined by the gate metal to nanotube work function difference and any insulatornanotube surface states.Because V fb depends on specifics of experimental conditions, all results will be plotted as a function of V G Ј except otherwise specified.By solving Eqs.͑1͒ and ͑2͒ self-consistently, the Q L (V G ) relation is obtained and the gate capacitance is C G ϭϪdQ L /dV G .This procedure is analogous to the one commonly used to compute MOS C G versus V G characteristics. 6efore the C G versus V G characteristic can be evaluated, the insulator capacitance must be specified.There is a simple, analytical expression for the coaxial geometry, 13 but planar capacitors require a numerical solution of twodimensional Poisson equation because two different dielectric constants above the metal plate ͑the insulator and air͒ invalidate the simple, analytical expression.The numerical solution was first evaluated for a classical conducting cylinder on the top of an infinite conducting plane with a uniform dielectric material between them, and the result agreed well with the exact analytical solutions. 13The single nanotube planar geometry, which has two dielectric materials ͓case ͑i͒ in Fig. 1͔ was then simulated.Two limits were considered: ͑1͒ a classical distribution of charge in the nanotube, which assumes the charge redistribute itself to establish an equal potential over the nanotube like a classical metal and ͑2͒ a single subband quantum distribution, which assumes that the charge distributes symmetrically around the nanotube.In the classical limit, we find C ins ϭ0.61 pF/cm and in the quantum limit, C ins ϭ0.53 pF/cm.The significant difference between the classical and quantum limits occurs because the quantum charge distribution ͑the center of the nanotube͒ is located further from the metal gate than is the classical charge centroid, and the nanotube diameter is comparable to t ins .Note that in most of the experimental planar nanotube capacitors explored to date 1,3 the difference between the classical and quantum limits will be small because the nanotube diameter ͑typically ϳ1 nm͒ is much smaller than insulator thickness ͑typically ϳ100 nm͒.The difference may become important, however, for the very thin insulators that will be used near the scaling limit.
Figure 2 shows the insulator capacitance of an array of parallel nanotubes ͓case ͑ii͒ in Fig. 1͔ versus the nanotube density, ϭ1/S, where S is the spacing between neighboring nanotubes.For small packing densities, the capacitance per unit area is proportional to the packing density.The largest capacitance per unit area ͑still 20%-50% below C ins of the planar silicon MOS capacitor͒ is achieved when the tubes are close packed, but increasing the normalized packing density above 0.5, does not result in the proportional increase of capacitance because each nanotube images to a narrower width and, therefore, a smaller fraction of the charge on the gate.When the nanotubes are closely packed, the capacitance per tube decreases due to the screening of the gate charge by the neighboring nanotubes. 14gure 3͑a͒ shows the one-dimensional ͑1D͒ charge density Q L as a function of the effective gate voltage V G Ј for the coaxial nanotube capacitor, which provides the optimum geometry for gate control in a MISFET. 15The charge density is approximately linear with gate voltage above the threshold voltage and can, therefore be expressed as Q L ϷC G (V G ϪV T ).The effective gate capacitance per unit length, C G Ϸ1.65 pF/cm, is only 80% of the insulator capacitance, C ins ϭ2.03 pF/cm, because the gate capacitance is the series combination of the insulator and nanotube capacitance.For very large gate voltages ͑where our semiclassical treatment needs to be critically examined͒, electrons occupy the second conduction band as shown in the inset of Fig. 3͑a͒.The subband spacing decreases with increasing nanotube diameter, but for typical diameters of about 1 nm and operating voltages of Ͻ0.5 V, only a single subband will be occupied.The one-subband approximation, therefore, can be used in the calculation.
Figure 3͑b͒ shows the computed C G versus V G characteristic of the coaxial nanotube capacitor.The striking difference from that for a MOS capacitor on an intrinsic substrate is due to the 1D DOS of the nanotube.The origin of local maxima is apparent when the nanotube capacitance is calculated at zero temperature C CNT (V CNT )ϭϪdQ L /dV CNT ϭe 2 D(eV CNT ), where D(E) is the DOS of the nanotube.Although the peaks in the 1D DOS are smoothed out by temperature, and the insulator capacitor in series, they still display local maximums on the C -V curve at room temperature.Experimental measurement of C -V curves, especially at low temperature using liquid-ion gating 9 which provides a high insulator capacitance, could generate useful diagnostic information on the DOS of the nanotube.
Figure 4 is an attempt to compare silicon MOS capacitors with carbon nanotube MIS capacitors.The MOS C G versus V G characteristic was computed by a self-consistent Schro ¨dinger-Poisson solver so that quantum confinement effects were included. 16The same threshold voltage V T , and the power supply voltage V DD , were assumed for all capacitors.On the left axis, we show that the effective gate capacitance of the nanotube array ͑the slope of the curve above threshold͒ is 66% of that of the silicon MOS capacitor because geometrical effects and quantum charge distribution reduce the insulator capacitance, as discussed earlier.͑For thicker gate insulator, a planar nanotube capacitor can outperform the corresponding silicon MOS capacitor because the capacitance decreases more slowly with the insulator thickness in the nanotube case. 3 ͒ The performance of planar nanotube capacitors may be improved by embedding nanotubes inside the gate insulator, 14 which results in comparable performance to the silicon, planar MOS capacitor.On the right axis, we compare the charge for a single tube in a planar geometry, case ͑i͒ in Fig. 1, to that in a coaxial geometry.The results show a clear advantage for the coaxial geometry and suggest that careful electrostatic design should be important for CNTFETs.
In summary, we have presented numerical studies of the MIS electrostatics of carbon nanotube capacitors and have shown that the capacitance versus voltage characteristics are quite different from those of standard, planar, silicon MOS capacitors.The difference arises from the 1D density of states in the nanotube, which leads to local maxima in the C G versus V G characteristic.We show that the planar nanotube capacitors offer comparable performance to the silicon MOS capacitors, but the coaxial gate geometry promises significantly higher performance.These results support a recent study based on a drift-diffusion analysis, which suggests that CNTFETs can be competitive with MOSFETs. 3 The electrostatic calculations also allow us to estimate the upper-limit on-current of CNTFETs based on a simple 1D model. 17,18is material is based upon work supported by the National Science Foundation under Grant No. 0085516.Helpful discussions with M. P. Anantram of NASA Ames Research Center and P. McEuen, Cornell, through the MARCO /DARPA Focus Center on Materials, Structures, and Devices are also acknowledged.

FIG. 1 .
FIG.1.Three geometries of nanotube MIS capacitors: ͑i͒ the single nanotube planar capacitor, ͑ii͒ a periodic array of nanotubes, and ͑iii͒ the coaxially gated capacitor.Nanotube diameter Dϭ1 nm, insulator thickness t ins ϭ1 nm, and a dielectric constant ins ϭ4 are the same for all capacitors.

FIG. 2 .
FIG.2.The insulator capacitance C ins versus the tube density ͑normalized to max ϭ1/D, the close-packed case͒ for an array of parallel nanotubes, compared to C ins ϭ ins 0 /t ins of the MOS capacitor ͑dotted line͒.The solid line assumes classical charge distribution, and dash line one subband quantum limit.

FIG. 4 .
FIG.4.Charge density vs. gate voltage V G .On the left axis, the closepacked array of nanotubes ͑dashed line͒ is compared to the silicon MOS capacitor ͑solid line͒.On the right axis, the coaxially gated capacitor ͑solid line with circles͒ is compared to the single nanotube planar geometry ͑dashed with circles͒.To make a fair comparison, the gate workfunction of each capacitor is adjusted to produce a common threshold voltage, V T Ϸ0.1 V.