Keywords
Undetectable faults, Design-For-Manufacture, Fault Clusters, Sub-circuits
Presentation Type
Poster
Research Abstract
Due to shrinking feature sizes, the number of defects in electronic chips has risen. These defects can be modeled as logic faults. Tests are applied to check whether or not a fault is present. Faults are not always present, but always need to be tested for. If a test for a fault does not exist, the fault is called undetectable. Undetectable faults leave uncovered defect sites in the circuit. It has been observed that undetectable faults cluster in sub-circuits of benchmark circuits. This implies that certain sub-circuits are uncovered or less covered than others by a test set for all the modeled faults. Design-For-Manufacturability (DFM) guidelines were created which if followed during manufacturing, can help avoid potential defects. DFM guidelines are not followed if they conflict with other constraints such as area or performance. This implies that defects are not avoided even if the possibility of their occurrence can be predicted. This research involves resynthesizing sub-circuits by using an algorithm in order to reduce the number of undetectable internal faults in them and break the fault clusters. It was observed that by replacing one instance in one cell type in every iteration, the number of undetectable internal faults were successfully reduced. It was also observed that in slightly larger circuits, the number of faults increased at the beginning of every new cycle due to an optimization step in the tool. It can thus be concluded that it is possible to break down the undetectable fault clusters using resynthesis.
Session Track
Data Trends and Analysis
Recommended Citation
Athmaram Swaminathan,
"Resynthesis Algorithm for Avoiding Undetectable Faults based on Design-For-Manufacturability Guidelines"
(August 3, 2017).
The Summer Undergraduate Research Fellowship (SURF) Symposium.
Paper 143.
https://docs.lib.purdue.edu/surf/2017/presentations/143
Resynthesis Algorithm for Avoiding Undetectable Faults based on Design-For-Manufacturability Guidelines
Due to shrinking feature sizes, the number of defects in electronic chips has risen. These defects can be modeled as logic faults. Tests are applied to check whether or not a fault is present. Faults are not always present, but always need to be tested for. If a test for a fault does not exist, the fault is called undetectable. Undetectable faults leave uncovered defect sites in the circuit. It has been observed that undetectable faults cluster in sub-circuits of benchmark circuits. This implies that certain sub-circuits are uncovered or less covered than others by a test set for all the modeled faults. Design-For-Manufacturability (DFM) guidelines were created which if followed during manufacturing, can help avoid potential defects. DFM guidelines are not followed if they conflict with other constraints such as area or performance. This implies that defects are not avoided even if the possibility of their occurrence can be predicted. This research involves resynthesizing sub-circuits by using an algorithm in order to reduce the number of undetectable internal faults in them and break the fault clusters. It was observed that by replacing one instance in one cell type in every iteration, the number of undetectable internal faults were successfully reduced. It was also observed that in slightly larger circuits, the number of faults increased at the beginning of every new cycle due to an optimization step in the tool. It can thus be concluded that it is possible to break down the undetectable fault clusters using resynthesis.